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From algorithms to RTL: high-performance, reliable digital hardware for commercial applications.
Official website · GitHub organization · Organization profile
This repository contains OpenRTL's public organization profile, with a separate Markdown file for each language. Explore released Chisel/SystemVerilog hardware, reproducible verification evidence, and custom ASIC/FPGA development services on the organization homepage.
Our focus is original MIT-licensed digital hardware, including compute accelerators, controllers and interfaces, with commercial-grade performance and reliability as engineering goals. Project documentation defines the verified configurations, measured results and integration limits.
OpenZK accelerator catalogue · OpenETH Ethernet RTL and software · OpenImage image-codec hardware catalogue · Custom ASIC/FPGA development
Profile text is available under the MIT License. Linked projects retain the licenses and third-party notices in their respective repositories.